A solid state drive (SSD) is a data storage device that utilizes solid-state memory to retain data in nonvolatile memory chips. NAND-based flash memories are widely used as the solid-state memory storage in SSDs due to their compactness, low power consumption, low cost, high data throughput and reliability. SSDs commonly employ several NAND-based flash memory chips and a flash controller to manage the flash memory and to transfer data between the flash memory and a host computer.
While NAND-based flash memories are reliable, they are not inherently error-free and often rely on error correction coding (ECC) to correct raw bit errors in the stored data. One commonly employed error correction code for nonvolatile memory storage modules, such as SSDs, is the low-density parity-check (LDPC) code. An LDPC code is a linear error correcting code having a parity check matrix with a small number of nonzero elements in each row and column. Soft-decision message passing algorithms are known in the art for decoding data encoded with LDPC error correction codes, such as the sum-product algorithm (SPA) and the min-sum algorithm. These soft-decision message passing algorithms are iterative in nature and attempt to decode the encoded data by assigning probability metrics to each bit in an encoded code word. The probability metrics indicate a reliability of each bit, that is, how likely it is that the bit read from the memory is not in error. These probability metrics are commonly referred to log likelihood ratios (LLRs) in the case of LDPC decoding. These LLRs values are often stored in LLR look-up tables, which are accessible by the NAND flash controller. To read the LDPC encoded data from the memory storage, a set of reference voltages are selected based upon the number of reads required and the number of bits used to represent the LLR value. The set of reference voltages selected determines the LLR values selected from the LLR look-up table.
The ability of an error correction circuit, such as an LDPC error correction circuit, to correct errors in a noisy channel is a critical performance parameter of a nonvolatile memory storage system. It is known in the art to test the performance of error correction circuits under an additive white Gaussian noise (AWGN) channel by generating AWGN samples that are used to access the LLR look-up tables of the nonvolatile memory storage system. However, noise generation circuits and techniques currently known in the art are very complex, requiring extensive mathematical functions to implement in logic gates. The noise generation circuits known in the art require a large area of space and the size of the circuitry increases as the number of required noise samples per clock cycle increases. As a result of the size and complexity of the noise generation circuits currently known in the art, it is commonly necessary to implement the AWGN generation circuitry in a dedicated FPGA (field-programmable gate array) or ASIC (application-specific integrated circuit) that is distinct from the encoding and decoding circuitry of the nonvolatile memory storage system.
Accordingly, what is needed in the art is an improved system and method for generating random noise samples for testing the error correction code circuitry of a nonvolatile memory system.